"Mr. Krishna Rao, Sr. Director Physical Design having overall 25+ Years of Industry Experience in VLSI Backend (Netlist To GDSII). With his infinite energy managed a Team of 100+ Engineers. Actively Participated in 40+ SoC TO across the Tech nodes (135 um to 3 nm). Got ample of experience in Die Size Optimization, Feedthrus Assessment and optimizations, Block Shape/Area, and Partition releases. He is Expertised in Flow Development and Input Collateral, Signoff, and Tapeout Reviews. Std.Cell/Block Level Characterization. Block Data Releases and SoC Integration."

- Krishna Rao, Director

"Ramasrinivas working as VLSI Backend Design Engineer. He has more than 1.5 Decades of experience in multiple successful product startups and MNCs. He has technical experience in Physical Design, DFT and Verification of aggressive SoCs in advanced nodes like 28nm, 14nm, 10nm, 7nm, 5nm and 3nm. Most of his work is done on networking, mobile, processor and AI chipsets. He has nurtured and built teams to successfully design, deliver and support SoCs and SoC based systems to Tier-1 customers worldwide."

"It is our esteemed honor to have him as the Mentor who will be guiding the budding VLSI Engineers in our Institute."

- Ramasrinivas, Mentor

"Mr. RAJU , VLSI backend design engg with Overall 12+ Years of Industry Experience in VLSI Backend, Synthesis. He has technical experience in physical design, and verification of complex SoCs in advanced nodes like 28nm, 14nm, 10nm, 7nm, 5nm and 3nm. With his Technical capabilities managed a Team of 15+ Engineers. He is Expertised in Flow Development and Input Collateral, Signoff, and Tapeout Reviews. He has built teams to successfully design, deliver and support SoCs and SoC based systems to Tier-1 customers worldwide."

- Raju, Director

"Mr.Srikiran , VLSI Backend Design Engineer with Overall 13+ Years of Industry Experience in VLSI Backend, Synthesis, and DFT. Managing a Team of 12+ Engineers and 3 Leads with 6 Direct Reports and trained many in the Backend domain. Being Expertise in SOC Level Implementation ,Taped-out 4 SOCs ( 2 Test Chips ). Possess complete knowledge and Experience in Netlist to GDSII complete flow. Accomplished 20+ Tape-outs successfully with Technology ranging from 130nm to 3nm which includes 4 SOC Levels. Experience in STA Closure for 5 Blocks which includes Constraints Validation/Correction, Timing Correlation PD Tool to STA Signoff Tool, ECO Generation using Tweaker/DMSA for 200+ Scenarios and ECO Implementation.Have competent in working on DFT - Did Scan Insertion, Coverage Improvement using Visualizer, MBIST Insertion, TDL Generation and Verification, JTAG Insertion, etc., Run simulations for testing the Vectors and finding the faults."

- Srikiran, Mentor

"Amala M Educator, with 12+ years of experience in teaching field in a reputed Engg College, with practical and conceptual teaching knowledge of various subjects like Digital Electronics, VLSI Design, Embedded systems ,Electronics etc.. Having guided a number of academic projects in various fields of Electronics Having been trained in DFT and STA, with working experience in Cadence and synopsys EDA tool. With my good experience and knowledge guiding and training the candidates with basic foundations of electronics to the real world of Industry."

- Amala, Educator